The maximum a-posteriori probability (MAP) algorithm is used in a number of coding schemes to improve the performance of communication systems. Maximum a-posteriori probability (MAP) decoders are used in, for example, turbo code-based radio frequency (RF) transceivers. Turbo coding is a powerful forward error correction (FEC) algorithm that achieves a coding gain close to the Shannon limit. Turbo encoders and turbo decoders have been adopted for use in the physical layers of a number of wireless standards, including WCDMA, CDMA2000, IEEE-802.16e (i.e., WiBro) and others. Thus, MAP decoders are implemented in, for example, WCDMA 8PCCC turbo decoders and in 802.16/Wibro CTC turbo decoders.
A software-defined radio (SDR) device uses reconfigurable hardware that may be programmed over-the-air to operate under different wireless standards. For example, an SDR transceiver in a wireless laptop computer or PDA may be configured by different software loads to operate in an IEEE-802.11x wireless network, a CDMA2000 wireless network, an OFDM/OFDMA wireless network, a GSM wireless network, or other types of networks. Many of these wireless standards require the use of turbo decoders or other decoders that are based on maximum a-posteriori probability (MAP) decoders.
However, conventional decoders have significant drawbacks with respect to SDR applications. Turbo decoders and other types of decoders are optimized for decoding under only one or two specific standards. Conventional designs use different MAP decoders to support each standard separately. For example, a MAP decoder calculates three values: alpha (α), beta (β), and lambda (γ). Normally, three distinct hardware blocks are used to calculate these values. This increases power consumption and uses a large amount of die space.
If an SDR device is required to support many wireless standards, more than one decoder must be implemented in the SDR device. This leads to a complex transceiver design that makes inefficient use of chip space and has high power dissipation. This also increases development cost and time-to-market (TTM). Additionally, some of the newer wireless standards operate at relatively high data rates (e.g., WiBro, HSPDA, and the like). A decoder that is optimized in terms of speed and power consumption for a low data rate standard is unlikely to be optimized in terms of speed and power consumption for a high data rate standard, and vice versa. Thus, conventional decoder designs are not suitable for use in SDR applications.
The higher target data rates, the iterative nature of turbo decoding for optimal performance, and certain other factors indicate that some parallelism is necessary in turbo decoder design. A sliding window (SW) may be used to split a block into sub-blocks that may be decoded in parallel. Each sub-block requires separate memory to maximize throughput when reading or writing extrinsic information (i.e., lambda (λ) values).
The reading or writing should be in a permuted order according to the interleaver pattern. However, the pattern will very likely introduce collisions when two or more extrinsic values are read from or written to the same memory address during the same clock cycle. Such collisions adversely affect the performance of a parallel turbo decoder. Conventional solutions duplicate the interleaved data in each memory in order to avoid collisions. However, this results in increased memory size and increased power.
Therefore, there is a need in the art for an improved reconfigurable decoder for use in a software-defined radio (SDR) system. In particular, there is a need for a maximum a-posteriori probability (MAP) decoder that may be implemented in a reconfigurable decoder that operates under different wireless standards. More particularly, there is a need for an interleaved function that avoids memory collisions when reading or writing extrinsic information (i.e., lambda (λ) values) during execution of the MAP algorithm.